The communications industry is rapidly changing to adjust to emerging technologies and ever increasing customer demand. This customer demand for new applications and increased performance of existing applications is driving communications network and system providers to employ networks and systems having greater speed and capacity (e.g., greater bandwidth). In trying to achieve these goals, a common approach taken by many communications providers is to use packet switching technology. Increasingly, public and private communications networks are being built and expanded using various packet technologies, such as Internet Protocol (IP).
Many packet switching and other communications systems have data that is time or latency sensitive that must be communicated between internal or external devices. For example, in a packet switching system, ingress packet processors transmit packets via a switching fabric to destination packet processors. Depending on traffic and load patterns, a particular packet processor might receive more packets than it can handle, and thus, need to inform the sending (or all) packet processors to stop sending it more packets at the present time.
In a known system, this flow control information is inserted in a field of the header of a packet sent between components, with a check code for error detection or correction located at the end of the packet. Thus, the packet must completely be received before the flow control information can be used after its validity is verifying based on the check code. This causes the flow control information to age an additional time for the data in the payload of the packet to be sent.
One known implementation uses multiple check codes for a packet, such as one for the header and one for the rest or entire packet, so that the header can be processed before the entire packet is received. However, these multiple and smaller check codes do not provide as much data protection as a single check code having the same number of bits as all the smaller check codes combined. Thus, in terms of bit and bandwidth cost, it is desirable to have a single, longer check code.
Moreover, the number of packets a destination packet processor will receive after identification of the overload conditions is directly related to the time it takes to communicate the flow control information and for the sending devices to react to it. Thus, the size of the packet buffers an egress packet processor must have to hold these packets is directly related to the time required from identification of the overload condition until the sending devices react to this information. New methods and apparatus are desired which may reduce this latency.